LIFO
後進先出(堆疊)記憶體
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LIFO is
generic(
WIDTH : natural := 8;
DEPTH : natural := 128
);
port(
I_DATA : in std_logic_vector(WIDTH - 1 downto 0); --Input Data Line
O_DATA : out std_logic_vector(WIDTH - 1 downto 0); --Output Data Line
I_RD_WR : in std_logic; --Input RD/~WR signal. 1 for READ, 0 for Write
O_FULL : out std_logic; --Output Full signal. 1 when memory is full.
O_EMPTY : out std_logic; --Output Empty signal. 1 when memory is empty.
clk : in std_logic;
rst : in std_logic
);
end entity LIFO;
architecture RTL of LIFO is
-- Helper Function to convert Boolean to Std_logic
function to_std_logic(B : boolean) return std_logic is
begin
if B = false then
return '0';
else
return '1';
end if;
end function to_std_logic;
type memory_type is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
signal memory : memory_type;
begin
main : process(clk, rst) is
variable stack_pointer : integer range 0 to DEPTH := 0;
variable EMPTY, FULL : boolean := false;
begin
--Async Reset
if rst = '1' then
memory <= (others => (others => '0'));
EMPTY := true;
FULL := false;
stack_pointer := 0;
elsif rising_edge(clk) then
if I_RD_WR = '1' then
-- READ
if not EMPTY then
O_DATA <= memory(stack_pointer);
stack_pointer := stack_pointer - 1;
end if;
else
if stack_pointer < 16 then
stack_pointer := stack_pointer + 1;
memory(stack_pointer - 1) <= I_DATA;
end if;
end if;
-- Check for Empty
if stack_pointer = 0 then
EMPTY := true;
else
EMPTY := false;
end if;
-- Check for Full
if stack_pointer = DEPTH then
FULL := true;
else
FULL := false;
end if;
end if;
O_FULL <= to_std_logic(FULL);
O_EMPTY <= to_std_logic(EMPTY);
end process main;
end architecture RTL;